Transistor Sizing in Order to Hardening CMOS circuit against Soft Error
نویسندگان
چکیده
منابع مشابه
Transistor sizing for low power CMOS circuits
A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area. Analytical formulation for the power dissi...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2013
ISSN: 0975-8887
DOI: 10.5120/13545-1337